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INTEGRATED CIRCUITS
DATA SHEET
PCF2116 family LCD controller/drivers
Product specification Supersedes data of 1996 Oct 25 File under Integrated Circuits, IC12 1997 Apr 07
Philips Semiconductors
Product specification
LCD controller/drivers
CONTENTS 1 2 3 3.1 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 9 9.1 9.2 FEATURES APPLICATIONS GENERAL DESCRIPTION Packages ORDERING INFORMATION BLOCK DIAGRAM PINNING PIN FUNCTIONS RS: register select (parallel control) R/W: read/write (parallel control) E: data bus clock DB0 to DB7: data bus C1 to C60: column driver outputs R1 to R32: row driver outputs VLCD: LCD power supply V0: VLCD control input OSC: oscillator SCL: serial clock line SDA: serial data line SA0: address pin T1: test pad FUNCTIONAL DESCRIPTION LCD supply voltage generator, PCF2114x and PCF2116x LCD supply voltage generator, PCF2116K Character generator ROM (CGROM) LCD bias voltage generator Oscillator External clock Power-on reset Registers Busy Flag Address Counter (AC) Display data RAM (DDRAM) Character generator ROM (CGROM) Character generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Programming MUX 1 : 16 displays with the PCF2114x Programming MUX 1 : 32 displays with the PCF2114x Reset function INSTRUCTIONS Clear display Return home 2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 10 11 11.1 11.2 11.3 11.4 11.5 11.6 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 23 24
PCF2116 family
Entry mode set Display on/off control Cursor/display shift Function set Set CGRAM address Set DDRAM address Read busy flag and address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) Characteristics of the I2C-bus Bit transfer START and STOP conditions System configuration Acknowledge I2C-bus protocol LIMITING VALUES HANDLING DC CHARACTERISTICS DC CHARACTERISTICS (PCF2116K) AC CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION 8-bit operation, 1-line display using internal reset 4-bit operation, 1-line display using internal reset 8-bit operation, 2-line display I2C operation, 1-line display Initializing by instruction BONDING PAD LOCATIONS PACKAGE OUTLINE SOLDERING DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1997 Apr 07
Philips Semiconductors
Product specification
LCD controller/drivers
1 FEATURES 3
PCF2116 family
GENERAL DESCRIPTION
* Single chip LCD controller/driver * 1 or 2-line display of up to 24 characters per line, or 2 or 4 lines of up to 12 characters per line * 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese syllabary) and user defined symbols * On-chip: - generation of LCD supply voltage (external supply also possible) - generation of intermediate LCD bias voltages - oscillator requires no external components (external clock also possible) * Display data RAM: 80 characters * Character generator ROM: 240 characters * Character generator RAM: 16 characters * 4 or 8-bit parallel bus or 2-wire I2C-bus interface * CMOS/TTL compatible * 32 row, 60 column outputs * MUX rates 1 : 32 and 1 : 16 * Uses common 11 code instruction set * Logic supply voltage range, VDD - VSS: 2.5 to 6 V * Display supply voltage range, VDD - VLCD: 3.5 to 9 V * Low power consumption * I2C-bus address: 011101 SA0. 2 APPLICATIONS
The PCF2116 family of LCD controller/drivers consists of the PCF2116x, the PCF2114x and the PCF2116K. The term `PCF2116' is used to refer to all devices for common information. Specific information is given in separate paragraphs. The `x' in `PCF2116x' and `PCF2114x' represents a specific letter code for a character set in the character generator ROM (CGROM). The different character sets currently available are specified by the letters A, C, and G (see Figs 8 to 10). Other character sets are available on request. The PCF2116 is a low-power CMOS LCD controller and driver, designed to drive a split screen dot matrix LCD display of 1 or 2 lines by 24 characters or 2 or 4 lines by 12 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system power consumption. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The PCF2116 interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. To allow partial VDD shutdown the ESD protection system of the SCL and SDA pins does not use a diode connected to VDD. The PCF2116K differs from the other members of the family in that: * VLCD/VOP generation is different (see Section 8.1) * It is available with character set C only (see Fig.9).
* Telecom equipment * Portable instruments * Point-of-sale terminals. 4 ORDERING INFORMATION TYPE NUMBER(1) PCF2116xU/10 PCF2114xU/10 PCF2116xU/12 PCF2114xU/12 PCF2116xHZ Note 1. The letter `x' in the type number represents the letter of the required built-in character set: A, C or G. PACKAGE NAME - - - - chip on flexible film carrier chip on flexible film carrier chip with bumps on flexible film carrier chip with bumps on flexible film carrier DESCRIPTION VERSION - - - - SOT425-1
LQFP128 plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
1997 Apr 07
3
Philips Semiconductors
Product specification
LCD controller/drivers
5 BLOCK DIAGRAM
PCF2116 family
handbook, full pagewidth
C1 to C60 68, 65 to 38 35 to 5 60 BIAS VOLTAGE GENERATOR 93, 95, 97 COLUMN DRIVERS 6 60
R1 to R32 84 to 77, 115 to 122 76 to 69, 123 to 128, 1 and 4 32 ROW DRIVERS 32 SHIFT REGISTER 32-BIT
V LCD
DATA LATCHES 60
V LCD GENERATOR
SHIFT REGISTER 5 x 12-bit 5
PCF2116
V0 VDD V SS
92
CURSOR + DATA CONTROL 5 CHARACTER GENERATOR RAM (CGRAM) 16 CHARACTERS CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
104, 106
109, 112
OSCILLATOR
102
OSC
T1
111
8 DISPLAY DATA RAM (DDRAM) 80 CHARACTERS 7 ADDRESS COUNTER (AC) 7 INSTRUCTION DECODER 8 DATA REGISTER (DR) 8 7 BUSY FLAG 8 INSTRUCTION REGISTER (IR) 8 I/O BUFFER 4 105, 103, 98, 96 DB0 to DB3 94, 91, 89, 87 DB4 to DB7 E 4 108 110 R/W 113 RS 88 SCL 7
TIMING GENERATOR
DISPLAY ADDRESS COUNTER
POWER - ON RESET
90 SDA
107
MGA797 - 1
SA0
Fig.1 Block diagram (pin numbers for LQFP128 package).
1997 Apr 07
4
Philips Semiconductors
Product specification
LCD controller/drivers
6 PINNING SYMBOL R31 n.c. R32 C60 to C30 n.c. C29 to C2 n.c. C1 R24 to R17 R8 to R1 n.c. DB7 SCL DB6 SDA DB5 V0 VLCD1 DB4 VLCD2 DB3 VLCD3 DB2 n.c. OSC DB1 VDD2 DB0 VDD1 SA0 E VSS1 R/W T1 VSS2 RS n.c. R9 to R16 R25 to R30 LQFP128 1 2 and 3 4 5 to 35 36 and 37 38 to 65 66 and 67 68 69 to 76 77 to 84 85 and 86 87 88 89 90 91 92 93 94 95 96 97 98 99 to 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 to 122 123 to 128 FFC PAD 27 - 28 29 to 59 - 60 to 87 - 88 89 to 96 97 to 104 - 105 106 107 108 109 110 111 112 113 114 115 116 - 1 2 3 4 5 6 7 8 9 10 11 12 - 13 to 20 21 to 26 TYPE O - O O - O - O O O - I/O I I/O I/O I/O I I/O I/O I/O I/O I/O I/O - I I/O P I/O P I I P I I P I - O O not connected LCD row driver output
PCF2116 family
DESCRIPTION LCD row driver output
LCD column driver outputs 60 to 30 not connected LCD column driver outputs 29 to 2 not connected LCD column driver output 1 LCD row driver outputs LCD row driver outputs not connected 1 bit of 8-bit bidirectional data bus I2C-bus serial clock input 1 bit of 8-bit bidirectional data bus I2C-bus serial data input/output 1 bit of 8-bit bidirectional data bus control input for VLCD LCD supply voltage input/output 1 1 bit of 8-bit bidirectional data bus LCD supply voltage input/output 2 1 bit of 8-bit bidirectional data bus LCD supply voltage input/output 3 1 bit of 8-bit bidirectional data bus not connected oscillator/external clock input 1 bit of 8-bit bidirectional data bus supply voltage 2 1 bit of 8-bit bidirectional data bus supply voltage 1 I2C-bus address pin data bus clock input (parallel control) ground (logic) 1 read/write input (parallel control) test pad (connect to VSS) ground (logic) 2 register select input (parallel control) not connected LCD row driver outputs LCD row driver outputs
1997 Apr 07
5
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
107 SA0 106 VDD1
R31 n.c. n.c. R32 C60 C59 C58 C57 C56 C55 C54 C52 C51 C50 C49 C48 C47 C46 C45 C44
1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21
103 DB1 102 OSC 101 n.c. 100 n.c. 99 n.c. 98 DB2 97 VLCD3 96 DB3 95 VLCD2 94 DB4 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VLCD1 V0 DB5 SDA DB6 SCL DB7 n.c. n.c. R1 R2 R3 R4 R5 R6 R7 R8 R17 R18 R19 R20 R21 R22 R23 R24 C1 n.c. n.c. C2 64 C3
MBD451 - 1
128 R30
127 R29
126 R28
125 R27
124 R26
123 R25
122 R16
121 R15
120 R14
119 R13
118 R12
117 R11 116 R10
114 n.c.
handbook, full pagewidth
C53 12
PCF2116
C43 22 C42 23 C41 24 C40 25 C39 26 C38 27 C37 28 C36 29 C35 30 C34 31 C33 32 C32 33 C31 34 C30 35 n.c. 36 n.c. 37 C29 38 48 49 51 52 53 54 55 56 57 58 59 60 61 C6 62 C5 C28 39 C27 40 C26 41 C25 42 C24 43 C23 44 C22 45 C21 46 C20 47 C17 50 63 C4
C19
C18
C16
C15
C14
C13
C12
C11
C10
C9
C8
Fig.2 Pin configuration (LQFP128).
1997 Apr 07
6
C7
105 DB0 104 VDD2
110 R/W 109 VSS1
113 RS 112 VSS2
115 R9
111 T1
108 E
Philips Semiconductors
Product specification
LCD controller/drivers
7 7.1 PIN FUNCTIONS RS: register select (parallel control) 7.9 OSC: oscillator
PCF2116 family
RS selects the register to be accessed for read and write when the device is controlled by the parallel interface. RS = logic 0 selects the instruction register for write and the Busy Flag and Address Counter for read. RS = logic 1 selects the data register for both read and write. There is an internal pull-up on pin RS. 7.2 R/W: read/write (parallel control)
When the on-chip oscillator is used this pin must be connected to VDD. An external clock signal, if used, is input at this pin. 7.10 SCL: serial clock line
Input for the I2C-bus clock signal. 7.11 SDA: serial data line
Input/output for the I2C-bus data line. 7.12 SA0: address pin
R/W selects either the read (R/W = logic 1) or write (R/W = logic 0) operation when control is by the parallel interface. There is an internal pull-up on this pin. 7.3 E: data bus clock
The hardware sub-address line is used to program the device sub-address for 2 different PCF2116s on the same I2C-bus. 7.13 T1: test pad
The E pin is set HIGH to signal the start of a read or write operation when the device is controlled by the parallel interface. Data is clocked in or out of the chip on the negative edge of the clock. Note that this pin must be tied to logic 0 (VSS) when I2C-bus control is used. 7.4 DB0 to DB7: data bus
Must be connected to VSS. Not user accessible. 8 8.1 FUNCTIONAL DESCRIPTION (see Fig.1) LCD supply voltage generator, PCF2114x and PCF2116x
The bidirectional, 3-state data bus transfers data between the system controller and the PCF2116. DB7 may be used as the Busy Flag, signalling that internal operations are not yet completed. In 4-bit operations the 4 higher order lines DB4 to DB7 are used; DB0 to DB3 must be left open circuit. There is an internal pull-up on each of the data lines. Note that these pins must be left open circuit when I2C-bus control is used. 7.5 C1 to C60: column driver outputs
The on-chip voltage generator is controlled by bit G of the `Function set' instruction and V0. V0 is a high-impedance input and draws no current from the system power supply. Its range is between VSS and VDD - 1 V. When V0 is connected to VDD the generator is switched off and an external voltage must be supplied to pin VLCD. This may be more negative than VSS. When G = logic 1 the generator produces a negative voltage at pin VLCD, controlled by the input voltage at pin V0. The LCD operating voltage is given by the relationship: VOP = 1.8VDD - V0 Where: VOP = VDD - VLCD VLCD = V0 - (0.8VDD) When G = logic 0, the generated output voltage VLCD is equal to V0 (between VSS and VDD). In this instance: VOP = VDD - V0 When VLCD is generated on-chip the VLCD pin should be decoupled to VDD with a suitable capacitor. VDD and V0 must be selected to limit the maximum value of VOP to 9 V. Figure 3 shows the two generator control characteristics. 7
These pins output the data for pairs of columns. This arrangement permits optimized chip-on-glass (COG) layout for 4-line by 12 characters. 7.6 R1 to R32: row driver outputs
These pins output the row select waveforms to the left and right halves of the display. 7.7 VLCD: LCD power supply
Negative power supply for the liquid crystal display. This may be generated on-chip or supplied externally. 7.8 V0: VLCD control input
The input level at this pin determines the generated VLCD output voltage.
1997 Apr 07
Philips Semiconductors
Product specification
LCD controller/drivers
8.2 LCD supply voltage generator, PCF2116K 8.5 Oscillator
PCF2116 family
In the PCF2116K version, V0 is connected through an on-chip resistor (R0) to VLCD. Resistor R0 has a nominal value of 1 M and draws a typical current of 4 A from the pin V0. A constant voltage (equal to 1.34VDD) is always present across R0. The voltage range of the PCF2116K is between VSS and VDD - 0.5 V (see Fig.4). When V0 is connected to VDD the generator is switched off and an external voltage must be supplied to pin VLCD. This may be more negative than VSS. When G = logic 1 the generator produces a negative voltage at pin VLCD, controlled by the input voltage at pin V0. The LCD operating voltage is given by the relationship: VOP = 2.34VDD - V0 Where: VOP = VDD - VLCD VLCD = V0 - (1.34VDD) When G = logic 0, the generated output voltage VLCD is equal to V0 (between VSS and VDD). In this instance: VOP = VDD - V0 8.3 Character generator ROM (CGROM)
The on-chip oscillator provides the clock signal for the display system. No external components are required. Pin OSC must be connected to VDD. 8.6 External clock
If an external clock is to be used, it must be input at pin OSC. The resulting display frame frequency is given by fframe = 12304fosc . A clock signal must always be present, otherwise the LCD may be frozen in a DC state. 8.7 Power-on reset
The power-on reset block initializes the chip after power-on or power failure. 8.8 Registers
The PCF2116 has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as `Display clear' and `Cursor shift', and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written to, but not read, by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the Address Counter is written to the data register prior to being read by the `Read data' instruction. 8.9 Busy Flag
The standard character sets A, C and G are available for the PCF2114x and PCF2116x. Standard character set C is available for the PCF2116K. 8.4 LCD bias voltage generator
The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system power consumption. The optimum levels depend on the multiplex rate and are selected automatically when the number of lines in the display is defined. The optimum value of VOP depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships in Table 1.Using a 5-level bias scheme for 1 : 16 MUX rate allows VOP < 5 V for most LCD liquids. The effect on the display contrast is negligible. Table 1 Optimum values for VOP MUX RATE 1 : 16 1 : 32 1997 Apr 07 NUMBER OF BIAS LEVELS 5 6 8
The Busy Flag indicates the free/busy status of the PCF2116. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The Busy Flag is output to pin DB7 when RS = logic 0 and R/W = logic 1. Instructions should only be written after checking that the Busy Flag is logic 0 or waiting for the required number of clock cycles.
VOP/Vth 3.67 5.19
DISCRIMINATION Von/Voff 1.277 1.196
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
9 VOP 8 6 = VDD 7 VOP(max) = 1.8 x V DD
9V
G=1
5 6 4 5 3 4 3.5 0 2.5 VOP(min) = 0.8 x VDD 1
1
2
3
4
5
V0
6
MGA798
a. High-voltage mode VOP = 1.8VDD - V0.
9 VOP 8
7
G=0
6
5 5 4 3.5 0 4 1
6 = VDD
2
3
4
5
V0
6
MGA799
b. Buffer mode VOP = VDD - V0.
Fig.3 VOP as a function of V0 control characteristics.
1997 Apr 07
9
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
9 6 VOP 8 5 7
9V
G=1
4 = VDD 6
5 2.5 4 3.5 0 1 2
3 VOP(min) = 1.34 x VDD + 0.5
3
4
5
V0
6
MBH667
a. High-voltage mode VOP = 2.34VDD - V0.
9 VOP 8
7
G=0
6
5 5 4 3.5 0 4 1
6 = VDD
2
3
4
5
V0
6
MGA799
b. Buffer mode VOP = VDD - V0.
Fig.4 VOP as a function of V0 control characteristics (PCF2116K).
1997 Apr 07
10
Philips Semiconductors
Product specification
LCD controller/drivers
8.10 Address Counter (AC) 8.13
PCF2116 family
Character generator RAM (CGRAM)
The Address Counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the instructions `Set CGRAM address' and `Set DDRAM address'. After a read/write operation the Address Counter is automatically incremented or decremented by 1.The Address Counter contents are output to the bus (DB0 to DB6) when RS = logic 0 and R/W = logic 1. 8.11 Display data RAM (DDRAM)
Up to 16 user-defined characters may be stored in the character generator RAM. The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.8). Figure 11 shows the addressing principle for the CGRAM. 8.14 Cursor control circuit
The display data RAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations not used for storing display data can be used as general purpose RAM. The basic DDRAM-to-display mapping scheme is shown in Fig.5. With no display shift the characters represented by the codes in the first 12 or 24 RAM locations starting at address 00 in line 1 are displayed. Subsequent lines display data starting at addresses 20, 40, or 60 Hex. Figs 6 and 7 show the DDRAM-to-display mapping principle when the display is shifted. The address range for a 1-line display is 00 to 4F; for a 2-line display from 00 to 27 (line 1) and 40 to 67 (line 2); for a 4-line display from 00 to 13, 20 to 33, 40 to 53 and 60 to 73 for lines 1, 2, 3 and 4 respectively. For 2 and 4-line displays the end address of one line and the start address of the next line are not consecutive. When the display is shifted each line wraps around independently of the others (Figs 6 and 7). When data is written into the DDRAM wrap-around occurs from 4F to 00 in 1-line mode and from 27 to 40 and 67 to 00 in 2-line mode; from 13 to 20, 33 to 40, 53 to 60 and 73 to 00 in 4-line mode. 8.12 Character generator ROM (CGROM)
The cursor control circuit generates the cursor (underline and/or character blink as shown in Fig.12) at the DDRAM address contained in the Address Counter. When the Address Counter contains the CGRAM address the cursor will be inhibited. 8.15 Timing generator
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.16 LCD row and column drivers
The PCF2116 contains 32 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display, in accordance with the data to be displayed. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 13 and 14 show typical waveforms. In 1-line mode (1 : 16) the row outputs are driven in pairs: R1/R17, R2/R18 for example. This allows the output pairs to be connected in parallel, providing greater drive capability. Unused outputs should be left unconnected.
The character generator ROM generates 240 character patterns in 5 x 8 dot format from 8-bit character codes. Figures 8 to 10 show the character sets currently available.
1997 Apr 07
11
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
Display handbook, 4 columns Position (decimal)
1
2
3
4
5
22 23 24
non-displayed DDRAM addresses
4C 4D 4E 4F
00 01 02 03 04
15 16 17 18 19
DDRAM Address (hex)
1-line display non-displayed DDRAM address
00 01 02 03 04 15 16 17 18 19 24 25 26 27
DDRAM Address (hex)
line 1
40 41 42 43 44
55 56 57 58 59
64 65 66 67
MLA792
line 2
2-line display
handbook, 4 columns
non-displayed DDRAM addresses 2 3 4 5 6 7 8 9 10 11 12 line 1
1
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33
line 2
DDRAM Address (hex)
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53
line 3
60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73
line 4
4 line display
MLA793
Fig.5 DDRAM-to-display mapping; no shift.
1997 Apr 07
12
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
Display Position (decimal) DDRAM Address (hex)
1
23
4
5
22 23 24
14 15 16
Display Position (decimal) DDRAM Address (hex)
line 1
1
23
4
5
22 23 24
16 17 18
4F 00 01 02 03
01 02 03 04 05
1-line display
1-line display
27 00 01 02 03
14 15 16
01 02 03 04 05
16 17 18
line 1
DDRAM Address (hex)
67 40 41 42 43
54 55 56
MLA802
line 2
DDRAM Address (hex)
41 42 43 44 45
56 57 58
MLA815
line 2
2-line display
2-line display
1234567
8 9 10 11 12 line 1
12
3 4 5 6 7 8 9 10 11 12 line 1
13 00 01 02 03 04 05 06 07 08 09 0A
01 02 03 04 05 06 07 08 09 0A 0B 0C
33 20 21 22 23 24 25 26 27 28 29 2A
line 2 DDRAM Address (hex)
21 22 23 24 25 26 27 28 29 2A 2B 2C
line 2
DDRAM Address (hex)
53 40 41 42 43 44 45 46 47 48 49 4A
line 3
41 42 43 44 45 46 47 48 49 4A 4B 4C
line 3
73 60 61 62 63 64 65 66 67 68 69 6A
line 4
61 62 63 64 65 66 67 68 69 6A 6B 6C
line 4
MLA816
4-line display
MLA803
4-line display
Fig.6 DDRAM-to-display mappi7ng; right shift.
Fig.7 DDRAM-to-display mapping; left shift.
1997 Apr 07
13
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth upper
lower 6 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MLB245 - 1
Fig.8 Character set `A' in CGROM: PCF2116A; PCF2114A.
1997 Apr 07
14
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
CG RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MLB895
Fig.9 Character set `C' in CGROM: PCF2116C; PCF2114C.
1997 Apr 07
15
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth upper
lower 6 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
CG RAM 1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MLB896
Fig.10 Character set `G' in CGROM: PCF2116G; PCF2114G.
1997 Apr 07
16
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
character codes (DDRAM data) 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0
7
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
MGA800 - 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th line will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.11 (bit 4 being at the left end). As shown in Figs 8 and 11, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `Set CGRAM address' instruction. Bit 6 can be set using the `Set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read busy flag and address' instruction.
Fig.11 Relationship between CGRAM addresses and data and display patterns.
1997 Apr 07
17
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
cursor 5 x 7 dot character font alternating display
MGA801
cursor display example
blink display example
Fig.12 Cursor and blink display examples.
1997 Apr 07
18
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
frame n
frame n 1
state 1 (ON) state 2 (ON)
ROW 1
VDD V2 V3 /V4 V5 V LCD VDD V2
ROW 9
V3 /V4 V5 V LCD VDD V2 V3 /V4 V5 V LCD VDD V2
1-line display (1:16)
ROW 2
COL 1
V3 /V4 V5 V LCD VDD V2 V3 /V4 V5 V LCD VOP
COL 2
0.25 VOP state 1 0 V 0.25 VOP VOP VOP
0.25 VOP state 2 0 V 0.25 VOP VOP
MGA802 - 1
123
16 1 2 3
16
Fig.13 Typical LCD waveforms; 1-line mode.
1997 Apr 07
19
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
frame n V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD V DD V2 V3 V4 V5 V LCD
frame n 1
state 1 (ON) state 2 (ON)
ROW 1
ROW 9
ROW 2
2-line display (1:32)
COL 1
COL 2
VOP
state 1
0.15 VOP 0V 0.15 VOP
VOP VOP
state 2
0.15 VOP 0V 0.15 VOP
VOP
MGA803 - 1
123
32 1 2 3
32
Fig.14 Typical LCD waveforms; 2-line mode.
1997 Apr 07
20
Philips Semiconductors
Product specification
LCD controller/drivers
8.17 Programming MUX 1 : 16 displays with the PCF2114x
PCF2116 family
With the `Function set' instruction M and N are set to 0, 0. Figures 15 to 17 show DDRAM addresses of the display characters. The second row of each table corresponds to either the right half of a 1-line display or to the second line of a 2-line display. Wrap around of data during display shift or when writing data is non-standard.
The PCF2114x can be used in: * 1-line mode to drive a 2-line display * 2 x 12 characters with MUX rate 1 : 16, resulting in better contrast. The internal data flow of the chip is optimized for this purpose.
handbook, full pagewidth
display position DDRAM address
1 00
2 01
3 02
4 03
5 04
6 05
7 06
8 07
9 08
10 09
11 0A
12 0B
display position DDRAM address
13 0C
14 0D
15 0E
16 0F
17 10
18 11
19 12
20 13
21 14
22 15
23 16
24 17
MLB899
Fig.15 DDRAM-to-display mapping; no shift (PCF2114x).
handbook, full pagewidth
display position DDRAM address
1 4F
2 00
3 01
4 02
5 03
6 04
7 05
8 06
9 07
10 08
11 09
12 0A
display position DDRAM address
13 0B
14 0C
15 0D
16 0E
17 0F
18 10
19 11
20 12
21 13
22 14
23 15
24 16
MLB900
Fig.16 DDRAM-to-display mapping; right shift (PCF2114x).
handbook, full pagewidth
display position DDRAM address
1 01
2 02
3 03
4 04
5 05
6 06
7 07
8 08
9 09
10 0A
11 0B
12 0C
display position DDRAM address
13 0D
14 0E
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
MLB901
Fig.17 DDRAM-to-display mapping; left shift (PCF2114x).
1997 Apr 07
21
Philips Semiconductors
Product specification
LCD controller/drivers
8.18 Programming MUX 1 : 32 displays with the PCF2114x 9 INSTRUCTIONS
PCF2116 family
To drive a 2-line by 24 characters MUX 1 : 32 display, use instruction `Function set' M, N to 0, 1. Note that the right half of the display needs mirrored column connection compared to a display driven by a PCF2116x. To drive a 4-line by 12 characters MUX 1 : 32 display the PCF2116x operating instructions apply. There is no functional difference between the PCF2114x and the PCF2116x in this mode. For such an application set M, N to 1, 1 with the `Function set' instruction. 8.19 Reset function
Only two PCF2116 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. The PCF2116 operation is controlled by the instructions shown in Table 3 together with their execution time. Details are explained in subsequent sections. Instructions are of 4 categories, those that:
The PCF2116 automatically initializes (resets) when power is turned on. After reset the chip has the following state. Table 2 STEP 1 2 display clear function set DL = 1 M, N = 0 G=0 8-bit interface 1-line display voltage generator; VLCD = V0 display off cursor off blink off +1 (increment) no shift State after reset DESCRIPTION
1. Designate PCF2116 functions such as display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instruction other than `Read busy flag and address' will be executed. Because the Busy Flag is set to logic 1 while an instruction is being executed, check to make sure it is on logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 3. An instruction sent while the Busy Flag is HIGH will not be executed.
3
display on/off control
D=0 C=0 B=0 I/D = 1 S=0
4 5
entry mode set
Default address pointer to DDRAM. The Busy Flag (BF) indicates the busy state (BF = logic 1) until initialization ends. The busy state lasts 2 ms. The chip may also be initialized by software. See Figs 28 and 29. I2C-bus interface reset
6
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1997 Apr 07 23
Philips Semiconductors
Table 3
Instructions (note 1)
LCD controller/drivers
INSTRUCTION NOP Clear display Return Home
RS 0 0 0
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 No operation.
DESCRIPTION
REQUIRED CLOCK CYCLES(2) 0 165 3
Clears entire display and sets DDRAM address 0 in Address Counter. Sets DDRAM address 0 in Address Counter. Also returns shifted display to original position. DDRAM contents remain unchanged. Sets cursor move direction and specifies shift of display. These operations are performed during data write and read. Sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B). Moves cursor and shifts display without changing DDRAM contents. Sets interface data length (DL), number of display lines (N, M) and voltage generator control (G). Sets CGRAM address. Sets DDRAM address. Reads Busy Flag (BF) indicating internal operation is being performed and reads Address Counter contents. Reads data from CGRAM or DDRAM. Writes data to CGRAM or DDRAM.
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control Cursor/display shift Function set
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 1 DL
1 S/C N
D R/L M
C 0 G
B 0 0
3 3 3
Set CGRAM address Set DDRAM address Read busy flag and address Read data Write data Notes
0 0 0
0 0 1
0 1 BF
1
ACG ADD AC
3 3 0
1 1
1 0
read data write data
3 3
PCF2116 family
Product specification
1. In the I2C-bus mode the DL bit is don't care. 8-bit mode is assumed. In the I2C-bus mode a control byte is required when RS or R/W is changed; control byte: Co, RS, R/W, 0, 0, 0, 0, 0; command byte: DB7 to DB0. 1 2. Example: fosc = 150 kHz, T cy = -------- = 6.67 s; 3 cycles = 20 s, 165 cycles = 1.1 ms. f osc
Philips Semiconductors
Product specification
LCD controller/drivers
Table 4 Command bit identities BIT I/D S D C B S/C R/L DL G N, (M = 0) PCF2116x PCF2114x N, (M = 1) BF Co 1 line x 24 characters; MUX 1 : 16 2 line x 12 characters; MUX 1 : 16 reserved end of internal operation last control byte, only data bytes to follow decrement display freeze display off cursor off character at cursor position does not blink cursor move left shift 4 bits voltage generator: VLCD = V0 0 increment display shift display on cursor on
PCF2116 family
1
character at cursor position blinks display shift right shift 8 bits voltage generator; VLCD = V0 - 0.8VDD 2 lines x 24 characters; MUX 1 : 32 2 lines x 24 characters; MUX 1 : 32 4 lines x 12 characters; MUX 1 : 32 internal operation in progress next two bytes are a data byte and another control byte
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
MGA804
Fig.18 4-bit transfer example.
1997 Apr 07
24
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7, IR3: instruction 7th bit, 3rd bit. AC3: Address Counter 3rd bit.
Fig.19 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
MGA806
Fig.20 Example of Busy Flag check timing sequence.
1997 Apr 07
25
Philips Semiconductors
Product specification
LCD controller/drivers
9.1 Clear display 9.4.2 C
PCF2116 family
`Clear display' writes space code 20 (hexadecimal) into all DDRAM addresses (The character pattern for character code 20 must be blank pattern). Sets the DDRAM Address Counter to logic 0. Returns display to its original position if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display (the first line if 2 or 4 lines are displayed). Sets entry mode I/D = logic 1 (increment mode). S of entry mode does not change. The instruction `Clear display' requires extra execution time. This may be allowed for by checking the busy-flag (BF) or by waiting until 2 ms has elapsed. The latter must be applied where no read-back options are foreseen, as in some chip-on-glass (COG) applications. 9.2 Return home
The cursor is displayed when C = logic 1 and inhibited when C = logic 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.12). 9.4.3 B
The character indicated by the cursor blinks when B = logic 1. The blink is displayed by switching between display characters and all dots on with a period of 1 second when fosc = 150 kHz (see Fig.12). At other clock frequencies the blink period is equal to 150 kHz/fosc. The cursor and the blink can be set to display simultaneously. 9.5 Cursor/display shift
`Return home' sets the DDRAM Address Counter to logic 0. Returns display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the display (the first line if 2 or 4 lines are displayed). I/D and S of entry mode do not change. 9.3 9.3.1 Entry mode set I/D
When I/D = logic 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor and blink are inhibited when the CGRAM is accessed. 9.3.2 S
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2 or 4-line displays, the cursor moves to the next line when it passes the last position (40 or 20 decimal) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the cursor shift. 9.6 9.6.1 Function set DL (PARALLEL MODE ONLY)
Defines interface data width when the parallel data interface is used. Data is sent or received in bytes (bits DB7 to DB0) when DL = logic 1, or in two 4-bit nibbles (DB7 to DB4) when DL = logic 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus(1). When using the I2C-bus interface the DL should not previously have been set to 0 using the parallel interface. 9.6.2 N, M
When S = logic 1, the entire display shifts either to the right (I/D = logic 0) or to the left (I/D = logic 1) during a DDRAM write. Thus it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing into or reading out of the CGRAM. When S = logic 0 the display does not shift. 9.4 9.4.1 Display on/off control D
Sets number of display lines.
The display is on when D = logic 1 and off when D = logic 0. Display data in the DDRAM are not affected and can be displayed immediately by setting D to logic 1.
(1) In a 4-bit application DB3 to DB0 are left open (internal pull-ups). Hence in the first `Function set' instruction after power-on, G and H are set to 1. A second `Function set' must then be sent (2 nibbles) to set G and H to their required values.
1997 Apr 07
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Philips Semiconductors
Product specification
LCD controller/drivers
9.6.3 G
PCF2116 family
After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D[4] to D[0] of CGRAM data are valid, bits D[7] to D[5] are `don't care'. 9.11 Read data from CGRAM or DDRAM
Controls the VLCD voltage generator characteristic. 9.7 Set CGRAM address
`Set CGRAM address' sets bit 0 to 5 of the CGRAM address (ACG in Table 3) into the Address Counter (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Only bits 0 to 5 of the CGRAM address are set by the `Set CGRAM address' instruction. Bit 6 can be set using the `Set DDRAM address' instruction or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `Read busy flag and address' instruction. 9.8 Set DDRAM address
Reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. The most recent `Set address' instruction determines whether the CGRAM or DDRAM is to be read. The `Read data' instruction gates the content of the data register (DR) to the bus while E = HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. Remark: the only three instructions that update the data register (DR) are: * `Set CGRAM address' * `Set DDRAM address' * `Read data' from CGRAM or DDRAM. Other instructions (e.g. `Write data', `Cursor/Display shift', `Clear display', `Return home') will not modify the data register content. 10 INTERFACE TO MICROCONTROLLER (PARALLEL INTERFACE) The PCF2116 can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB0 to DB7. Three further control lines E, RS, and R/W are required. In 4-bit mode data is transferred in two cycles of 4-bits each. The higher order bits (corresponding to DB4 to DB7 in 8-bit mode) are sent in the first cycle and the lower order bits (DB0 to DB3 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the Busy Flag check. 4-bit operation is selected by instruction. See Figs 18, 19 and 20 for examples of bus protocol. In 4-bit mode pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.
`Set DDRAM address' sets the DDRAM address (ADD in Table 3) into the Address Counter (binary A[6] to A[0]). Data can then be written to or read from the DDRAM. Hexadecimal address ranges. ADDRESS 00 to 4F 00 to 0B and 0C to 4F 00 to 27 and 40 to 67 00 to 13, 20 to 33, 40 to 53 and 60 to 73 9.9 FUNCTION 1-line by 24; 2114x/2116x 2-line by 12; 2114x 2-line by 24; 2114x/2116x 4-line by 12; 2114x/2116x
Read busy flag and address
`Read busy flag and address' reads the Busy Flag (BF). BF = logic 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = logic 0, so BF should be checked before sending another instruction. At the same time, the value of the Address Counter (AC in Table 3) expressed in binary A[6] to A[0] is read out. The Address Counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction. 9.10 Write data to CGRAM or DDRAM
Writes binary 8-bit data D[7] to D[0] to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous specification of CGRAM or DDRAM address setting.
1997 Apr 07
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Philips Semiconductors
Product specification
LCD controller/drivers
11 INTERFACE TO MICROCONTROLLER (I2C-BUS INTERFACE) 11.1 Characteristics of the I2C-bus 11.5 Acknowledge
PCF2116 family
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 11.2 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. 11.3 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 11.4 System configuration
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 11.6 I2C-bus protocol
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'.
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2116 READ and WRITE cycles is shown in Figs 25 to 27.
1997 Apr 07
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Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.21 Bit transfer.
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.22 Definition of START and STOP conditions.
1997 Apr 07
29
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.23 System configuration.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION
MBC602
1
2
8
9
clock pulse for acknowledgement
Fig.24 Acknowledgement on the I2C-bus.
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ull pagewidth
1997 Apr 07
Philips Semiconductors
LCD controller/drivers
acknowledgement from PCF2116
S CONTROL BYTE CONTROL BYTE A A DATA A0 DATA AP
S011101A0A1
0
slave address 2n Co Co 0 bytes 1 byte n
0 bytes
R/W
update data pointer
31
S 011101A0 0
MBH668
PCF2116 slave address R/W
PCF2116 family
Product specification
Fig.25 Master transmits to slave receiver; WRITE mode.
(1) Last data byte is a dummy byte (may be omitted).
Fig.26 Master reads after setting word address; write word address, set RS/RW; READ data.
handbook, full pagewidth
1997 Apr 07
acknowledgement from PCF2116 S
Philips Semiconductors
LCD controller/drivers
S011101A0A1
0
CONTROL BYTE
A
DATA
A011
CONTROL
A
DATA
(1)
A
slave address R/W Co
2n
0 bytes Co
2 bytes
acknowledgement from PCF2116
no acknowledgement from master
32
S
SLAVE ADDRESS
S A1A 0
DATA
A
DATA
1P
n bytes R/W
last byte update data pointer
MGA809 - 1
PCF2116 family
Product specification
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
acknowledgement from PCF2116
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA
A
DATA
1P
n bytes R/W
last byte update data pointer
MGA810 - 1
Fig.27 Master reads slave immediately after first byte; READ mode (RS previously defined).
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handbook, full pagewidth
1997 Apr 07
Philips Semiconductors
LCD controller/drivers
PROTOCOL
START CONDITION (S) BIT 6 (A6) ACKNOWLEDGE (A)
BIT 7 MSB (A7)
BIT 0 LSB R/W STOP CONDITION (P)
SDA
34
t LOW tr t HD;STA tf t HIGH t/fSCL
MGA811 - 1
t BUF
SCL
t SU;STO
PCF2116 family
Product specification
Fig.28 I2C-bus timing diagram; rise and fall times refer to VIL and VIH.
Philips Semiconductors
Product specification
LCD controller/drivers
12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VLCD VI VO II IO Ptot PO Tstg supply voltage LCD supply voltage input voltage OSC, V0, RS, R/W, E and DB0 to DB7 output voltage R1 to R32, C1 to C60 and VLCD DC input current DC output current total power dissipation power dissipation per output storage temperature PARAMETER MIN. -0.5 VDD - 11 VSS - 0.5 VLCD - 0.5 -10 -10 -50 - - -65
PCF2116 family
MAX. +8.0 VDD VDD + 0.5 VDD + 0.5 +10 +10 +50 400 100 +150 V V V V mA mA mA
UNIT
IDD, ISS, ILCD VDD, VSS or VLCD current
mW mW C
13 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices").
1997 Apr 07
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Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
14 DC CHARACTERISTICS VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD - 3.5 to VDD - 9 V; Tamb = -40 C to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD IDD IDD1 IDD2 supply voltage LCD supply voltage supply current external VLCD supply current 1 supply current 2 VDD = 5 V; VOP = 9 V; fosc = 150 kHz; Tamb = 25 C VDD = 3 V; VOP = 5 V; fosc = 150 kHz; Tamb = 25 C notes 1, 2 and 8 - VDD = 5 V; VOP = 9 V; fosc = 150 kHz; Tamb = 25 C VDD = 3 V; VOP = 5 V; fosc = 150 kHz; Tamb = 25 C notes 1 and 7 note 3 - 700 600 1100 900 A A note 1 - - 200 200 500 300 A A 2.5 VDD - 9 - - 6.0 VDD - 3.5 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IDD3
supply current 3
-
150
200
A
IDD IDD4 IDD5
supply current internal VLCD supply current 4 supply current 5
IDD6
supply current 6
-
500
800
A
ILCD VPOR Logic VIL1 VIH1 VIL(osc) VIH(osc) VIL(V0) VIH(V0) Ipu IOL(DB) IOH(DB) IL1
VLCD input current power-on reset voltage level
- -
50 1.3 - - - - - 0.15 - - -
100 1.8
A V
LOW level input voltage E, RS, R/W, DB0 to DB7 and SA0 HIGH level input voltage E, RS, R/W, DB0 to DB7 and SA0 LOW level input voltage OSC HIGH level input voltage OSC LOW level input voltage V0 HIGH level input voltage V0 pull-up current at DB0 to DB7 LOW level output current DB0 to DB7 HIGH level output current DB0 to DB7 leakage current OSC, V0, E, RS, R/W, DB0 to DB7 and SA0 VI = VSS
VSS 0.7VDD VSS VDD - 0.1 VSS 0.04
0.3VDD VDD VDD - 1.5 VDD VDD - 0.5 VDD 1.00 - - +1
V V V V V V A mA mA A
VDD - 0.05 - VOL = 0.4 V; VDD = 5 V 1.6 VOH = 4 V; VDD = 5 V VI = VDD or VSS -1.0 -1
1997 Apr 07
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Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
SYMBOL I2C-bus SDA, SCL VIL2 VIH2 IL2 Ci IOL(SDA) LCD outputs RROW RCOL Vtol1 Vtol2 Notes
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LOW level input voltage HIGH level input voltage leakage current input capacitance LOW level output current (SDA)
note 4 note 4 VI = VDD or VSS note 5
VSS 0.7VDD -1 -
- - - - -
0.3VDD VDD +1 7 -
V V A pF mA
VOL = 0.4 V; VDD = 5 V 3 note 6 note 7 note 2 - - - -
row output resistance R1 to R32 bias voltage tolerance R1 to R32 and C1 to C60 LCD supply voltage (VLCD) tolerance
1.5 3 20 40
3 6 130 300
k k mV mV
column output resistance C1 to C60 note 6
1. LCD outputs are open-circuit; inputs at VDD or VSS; V0 = VDD; bus inactive; internal or external clock with duty cycle 50% (IDD1 only). 2. LCD outputs are open-circuit; LCD supply voltage generator is on; load current at VLCD = 20 A. 3. Resets all logic when VDD < VPOR. 4. When the voltages are above or below the supply voltages VDD or VSS, an input current may flow; this current must not exceed 0.5 mA. 5. Tested on sample basis. 6. Resistance of output terminals (R1 to R32 and C1 to C60) with load current = 150 A; VOP = VDD - VLCD = 9 V; outputs measured one at a time; (external VLCD). 7. LCD outputs open-circuit; external VLCD. 8. Maximum value occurs at 85 C. 15 DC CHARACTERISTICS (PCF2116K) VDD = 2.5 to 6 V; VSS = 0 V; VLCD = VDD - 3.5 to VDD - 9 V; Tamb = -40 C to +85 C; unless otherwise specified. SYMBOL VDD VLCD V0 R0 Note 1. R0 has a temperature coefficient of resistance of +0.6%/K. PARAMETER supply voltage LCD supply voltage voltage generator control input voltage voltage generator control input resistance Tamb = 25 C; note 1 CONDITIONS MIN. 2.5 VDD - 9 VSS 700 TYP. - - - 1000 MAX. 6.0 VDD - 3.5 VDD - 0.5 1300 UNIT V V V k
1997 Apr 07
37
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
16 AC CHARACTERISTICS VDD = 2.5 to 6.0 V; VSS = 0 V; VLCD = VDD - 3.5 V to VDD - 9 V; Tamb = -40 C to +85 C; unless otherwise specified. SYMBOL fFR fosc PARAMETER LCD frame frequency (internal clock); note 1 external clock frequency MIN. 40 90 TYP. 65 150 MAX. 100 225 UNIT Hz kHz
Bus timing characteristics: Parallel Interface; notes 1 and 2 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2116) Tcy PWEH tASU tAH tDSW tHD Tcy PWEH tASU tAH tDHD tHD enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 100 ns ns ns ns ns ns
READ OPERATION (READING DATA FROM PCF2116 TO MICROCONTROLLER) enable cycle time enable pulse width address set-up time address hold time data delay time data hold time 500 220 50 25 - 20 - - 4.7 4.7 4 4.7 4 - - 250 0 4 ns ns ns ns ns ns
Timing characteristics: I2C-bus interface; note 2 fSCL tSW tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tSU;STO Notes 1. VDD = 5 V. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SCL clock frequency tolerable spike width on bus bus free time set-up time for a repeated START condition START condition hold time SCL LOW time SCL HIGH time SCL and SDA rise time SCL and SDA fall time data set-up time data hold time set-up time for STOP condition 100 100 - - - - - 1 0.3 - - - kHz ns s s s s s s s ns ns s
1997 Apr 07
38
Philips Semiconductors
Product specification
LCD controller/drivers
17 TIMING CHARACTERISTICS
PCF2116 family
book, full pagewidth
RS
VIH1 V IL1 t AS
VIH1 VIL1 t AH
R/W
V IL1 PW EH
VIL1 t AH VIL1 tH VIH1 VIL1
MLA798 - 1
E
VIH1 VIL1
VIH1 VIL1 t DSW VIH1 Valid Data VIL1 Tcy
DB0 to DB7
Fig.29 Parallel bus write operation sequence; writing data from microcontroller to PCF2116.
dbook, full pagewidth
RS
VIH1 V IL1 t AS
VIH1 VIL1 t AH VIH1
R/W
VIH1
PW EH E VIL1 VIH1 VIH1
t AH VIL1 VIL1
t DDR DB0 to DB7 VOH1 VOL1 Tcy
t DHR VOH1 VOL1
MLA799 - 1
Fig.30 Parallel bus read operation sequence; reading data from PCF2116 to microcontroller.
1997 Apr 07
39
Philips Semiconductors
Product specification
LCD controller/drivers
18 APPLICATION INFORMATION
PCF2116 family
handbook, 4 columns
P20 P21 P22 P80CL51
RS 32 R/W E PCF2116 60 R1 to R32 to LCD
P10 to P17
8
C1 to C60 DB0 to DB7
MGA812 - 1
Fig.31 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, 4 columns
P10 P11 P12
RS 32 R/W E PCF2116 60 R1 to R32 to LCD
P80CL51
P14 to P17
4
C1 to C60 DB4 to DB7
MGA813 - 1
Fig.32 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
V LCD 100 nF VDD 100 nF 100 k VDD OSC VO V SS PCF2116
R7 to R16 R25 to R32 R1 to R8 R17 to R24 16
16
2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) 60
MGA816 - 1
VSS
C1 to C60
60
DB0 to DB7 E
RS R/W
Fig.33 Typical application using parallel interface.
1997 Apr 07
40
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
V LCD 100 nF VDD 100 nF VDD VDD V SS 100 k VDD
R1 to R16
16
R17 to R24 OSC VO V SS C1 to C60 SA0 PCF2116 16
2 x 24 CHARACTER LCD DISPLAY (SPLIT SCREEN) 60 60
VDD
V LCD 100 nF VDD 100 nF 100 k VDD OSC VO V SS C1 to C60 SA0
MGA817 - 1
R1 to R16 PCF2114 16
2 x 12 CHARACTER LCD DISPLAY
60
V SS
VSS
SCL SDA
MASTER TRANSMITTER PCF84C81
Fig.34 Application using I2C-bus interface.
1997 Apr 07
41
Philips Semiconductors
Product specification
LCD controller/drivers
18.1 8-bit operation, 1-line display using internal reset 18.3
PCF2116 family
8-bit operation, 2-line display
Table 6 shows an example of a 1-line display in 8-bit operation. The PCF2116 functions must be set by the `Function set' instruction prior to display. Since the display data RAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and DDRAM contents remain unchanged, display data entered first can be displayed when the Return Home operation is performed. 18.2 4-bit operation, 1-line display using internal reset
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the eighth character is completed (see Table 7). Note that both lines of the display are always shifted together; data does not shift from one line to the other. 18.4 I2C operation, 1-line display
A control byte is required with most instructions (see Table 8). 18.5 Initializing by instruction
The program must set functions prior to 4-bit operation. Table 5 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2116 attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 5 step 3). Thus, DB4 to DB7 of the function set are written twice. Table 5 STEP 1 2
If the power supply conditions for correctly operating the internal reset circuit are not met, the PCF2116 must be initialized by instruction. Tables 9 and 10 show how this may be performed for 8-bit and 4-bit operation.
4-bit operation, 1-line display example; using internal reset INSTRUCTION power supply on (PCF2116 is initialized by the internal reset circuit) function set RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 Sets to 4-bit operation. In this instance operation is handled as 8-bits by initialization and only this instruction completes with one write. Sets to 4-bit operation, selects 1-line display and VLCD = V0. 4-bit operation starts from this point and resetting is needed. _ Turns on display and cursor. Entire display is blank after initialization. DISPLAY OPERATION Initialized. No display appears.
3
function set 0 0 0 0 0 0 0 0 1 0 0 0
4
display on/off control 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 _
5
entry mode set 0 0 Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM. Display is not shifted. Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. 42
6
write data to CGRAM/DDRAM 1 1 0 0 0 0 1 0 0 0 1 0 P_
1997 Apr 07
1997 Apr 07 43
Philips Semiconductors
Table 6 STEP 1 2
8-bit operation, 1-line display example; using internal reset (character set `A')
LCD controller/drivers
INSTRUCTION power supply on (PCF2116 is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION Initialized. No display appears.
Sets to 8-bit operation, selects 1-line display and VLCD = V0. Turns on display and cursor. Entire display is blank after initialization. Sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM. Display is not shifted. Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. Writes `H'. | | |
3
display mode on/off control 0
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
write data to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_
6 7
write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 PH_
8 9 10 11
write data to CGRAM/DDRAM 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 PHILIPS_ PHILIPS_ PHILIPS_ PHILIPS M_ Writes `S'. Sets mode for display shift at the time of write. Writes space. Writes `M'. entry mode set
PCF2116 family
write data to CGRAM/DDRAM write data to CGRAM/DDRAM
Product specification
1997 Apr 07 44
Philips Semiconductors
STEP 12
INSTRUCTION
DISPLAY | | |
OPERATION
LCD controller/drivers
13 14 15 16 17 Z18 19 20
write data to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 0 1 MICROKO MICROKO MICROKO ICROCO MICROCO MICROCO_ ICROCOM_ | | | Writes `O'. Shifts only the cursor position to the left. Shifts only the cursor position to the left. Writes `C' correction. The display moves to the left. Shifts the display and cursor to the right. Shifts only the cursor to the right. Writes `M'. cursor or display shift cursor or display shift write data to CGRAM/DDRAM cursor or display shift cursor or display shift write data to CGRAM/DDRAM
21
Return Home 0 0 0 0 0 0 0 0 1 0 PHILIPS M Returns both display and cursor to the original position (address 0).
PCF2116 family
Product specification
1997 Apr 07 45
Philips Semiconductors
Table 7 STEP 1 2
8-bit operation, 2-line display example; using internal reset
LCD controller/drivers
INSTRUCTION power supply on (PCF2116 is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 0 0 0 _ 0 0 0 0 0 0 1 1 1 0 _ 0 0 0 0 0 0 0 1 1 0
DISPLAY
OPERATION Initialized. No display appears. Sets to 8-bit operation, selects 2-line display and voltage generator off.
3
display on/off control
Turns on display and cursor. Entire display is blank after initialization.
4
entry mode set
Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM. Display is not shifted. Writes `P'. The DDRAM has already been selected by initialization at power-on. The cursor is incremented by 1 and shifted to the right. | | |
5
Write data to CGRAM/DDRAM w 1 0 0 1 0 1 0 0 0 0 P_
6
7
write data to CGRAM/DDRAM PHILIPS_ 1 0 0 1 0 1 0 0 1 1 PHILIPS 0 0 1 1 0 0 0 0 0 0 _
Writes `S'.
8
set DDRAM address
Sets DDRAM address to position the cursor at the head of the 2nd line.
PCF2116 family
9
write data to CGRAM/ DDRAM PHILIPS 1 0 0 1 0 0 1 1 0 1 M_ | | |
Writes `M'.
Product specification
10
1997 Apr 07 46
Philips Semiconductors
STEP 11
INSTRUCTION write data to CGRAM/ DDRAM
DISPLAY Writes `O'. PHILIPS
OPERATION
LCD controller/drivers
1 12
0
0
1
0
0
1
1
1
1
MICROCO_ Sets mode for display shift at the time of write. PHILIPS
write data to CGRAM/ DDRAM 0 0 0 0 0 0 0 1 1 1 MICROCO_ PHILIPS 1 0 0 1 0 0 1 1 0 1 ICROCOM_ | | |
13
write data to CGRAM/ DDRAM
Writes `M'. Display is shifted to the left. The first and second lines shift together.
14
15
return Home PHILIPS 0 0 0 0 0 0 0 0 1 0 MICROCOM
Returns both display and cursor to the original position (address 0).
PCF2116 family
Product specification
1997 Apr 07 47
Philips Semiconductors
Table 8 STEP 1 2
Example of I2C operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1) I2C BYTE I2C START slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 RS 0 1 R/W 0 X X X X X 1 0 1 0 0 1 Ack 1 Selects 1-line display and VLCD = V0; SCL pulse during acknowledge cycle starts execution of instruction. During the acknowledge cycle SDA will be pulled-down by the PCF2116. DISPLAY OPERATION Initialized. No display appears.
LCD controller/drivers
3
send a control byte for function set Co 0 Control byte sets RS and R/W for following data bytes.
4
function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1
5
display on/off control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 1 1 1 0 1 _ Turns on display and cursor. Entire display shows character Hex 20 (blank in ASCII-like character sets).
6
entry mode set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 START _ For writing data to DDRAM, RS must be set to 1. Therefore a control byte is needed. 0 0 0 1 1 0 1 _ Sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM. Display is not shifted.
7
I2C
8
slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 RS 1 1 R/W 0 X X X X X 1 0 1 0 0 1 Ack 1 _ Writes `P'. The DDRAM has been selected at power-up. The cursor is incremented by 1 and shifted to the right. _
9
send a control byte for write data Co 0
PCF2116 family
Product specification
10
write data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1 P_
1997 Apr 07 48
Philips Semiconductors
STEP 11 write data to DDRAM
I2C BYTE DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 1
DISPLAY Writes `H'. PH_ | | | |
OPERATION
LCD controller/drivers
12 to 15
16
write data to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 1 1 1 PHILIPS_ PHILIPS_ Writes `S'.
17 18
(optional I2C stop) I2C start + slave address for write (as step 8) control byte Co 1 RS 0 R/W 0 X X X X X Ack 1
PHILIPS_ Sets DDRAM address 0 in Address Counter. (also returns shifted display to original position. DDRAM contents unchanged). This instruction does not update the Data Register DDRAM content will be read from following instructions. The R/W has to be set to 1 while still in I2C-write mode.
19
Return Home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 0 1 0 1 PHILIPS
20
control byte for read Co 0 RS 1 R/W 1 X X X X X Ack 1 PHILIPS PHILIPS During the acknowledge cycle the content of the DR is loaded into the internal I2C interface to be shifted out. In the previous instruction neither a `Set address' nor a `Read data' has been performed. Therefore the content of the DR was unknown. 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA. MSB is DB7. During master acknowledge content of DDRAM address 01 is loaded into the I2C interface.
21 22
I2C START slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 1 1
PCF2116 family
PHILIPS
Product specification
23
read data: 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0 PHILIPS
1997 Apr 07 49
Philips Semiconductors
STEP 24
I2C BYTE read data: 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0
DISPLAY
OPERATION 8 x SCL; code of letter `H' is read first. During master acknowledge code of `I' is loaded into the I2C interface. No master acknowledge; After the content of the I2C interface register is shifted out no internal action is performed. No new data is loaded to the interface register, Data Register (DR) is not updated, Address Counter (AC) is not incremented and cursor is not shifted.
LCD controller/drivers
PHILIPS
25
read data: 8 x SCL + no master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 1 1 PHILIPS
26 Notes
I2C STOP
PHILIPS
1. X = don't care. 2. SDA is left at high-impedance by the microcontroller during the READ acknowledge.
PCF2116 family
Product specification
1997 Apr 07 50
Philips Semiconductors
Table 9
Initialization by instruction, 8-bit interface (note 1)
LCD controller/drivers
STEP power-on or unknown state | wait 2 ms after VDD rises above VPOR | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait 2 ms | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait more than 40 s | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | | RS 0 0 0 0 R/W 0 0 0 0 DB7 0 0 0 0 DB6 0 0 0 0 DB5 1 0 0 0 | Initialization ends Note 1. X = don't care. DB4 1 0 0 0 DB3 N 1 0 0 DB2 M 0 0 1 DB1 G 0 0 I/D DB4 1 DB3 X DB2 X DB1 X DB4 1 DB3 X DB2 X DB1 X DB4 1 DB3 X DB2 X DB1 X
DESCRIPTION
DB0 BF cannot be checked before this instruction. X Function set (interface is 8-bits long).
DB0 BF cannot be checked before this instruction. X Function set (interface is 8-bits long).
DB0 BF cannot be checked before this instruction. X Function set (interface is 8-bits long). BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3). DB0 Function set (interface is 8-bits long). Specify the number of display lines and voltage generator characteristic. 0 0 1 S Display off. Clear display. Entry mode set.
PCF2116 family
Product specification
1997 Apr 07 51
Philips Semiconductors
Table 10 Initialization by instruction, 4-bit interface. Not applicable for I2C-bus operation
LCD controller/drivers
STEP power-on or unknown state | wait 2 ms after VDD rises above VPOR | RS 0 wait 2 ms | RS 0 wait 40 s | RS 0 R/W 0 DB7 0 | RS 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 DB7 0 0 N 0 1 0 0 0 0 | Initialization ends DB6 0 0 M 0 0 0 0 0 1 DB5 1 1 G 0 0 0 0 0 I/D DB4 0 0 0 0 0 0 1 0 S Display off. DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1
DESCRIPTION
BF cannot be checked before this instruction. Function set (interface is 8-bits long).
BF cannot be checked before this instruction. Function set (interface is 8-bits long).
BF cannot be checked before this instruction. Function set (interface is 8-bits long). BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is the specified instruction time. (See Table 3). Function set (set interface to 4-bits long). Interface is 8-bits long. Function set (interface is 4-bits long). Specify number of display lines and voltage generator characteristic.
PCF2116 family
Clear display. Entry mode set.
Product specification
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
C1
DISPLAY LAYOUT: COLUMNS
15 31 45 45 31 15 1
PCF2116 column output numbers
1
31
61
91
120
LCD column numbers
C16
30 46
60 60
46 30
16
PCF2116 column output numbers
DISPLAY LAYOUT: ROWS
R8 to R1 R9 to R16
MGA814 - 1
R17 to R24 R32 to R25
2 x 24 character display
Fig.35 Example of 2 x 24 display layout (PCF2116x).
1997 Apr 07
52
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
DISPLAY LAYOUT: COLUMNS C1 15 46 60 PCF2116 column output numbers
1
31 DOT MATRIX LCD
60
LCD column numbers
C16
45
PCF2116 column output numbers
DISPLAY LAYOUT: ROWS R8 to R1 R9 to R16
MGA815 - 2
R17 to R24
R32 to R25
Fig.36 Example of 4 x 12 display layout (PCF2114x/PCF2116x).
1997 Apr 07
53
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
book, full pagewidth
display glass
dot matrix
COLUMN LAYOUT
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ROW LAYOUT 1 to 8 1 line by 24 characters display 16 to 9
MLB897
Fig.37 Display example (PCF2114x); 1-line by 24 characters.
1997 Apr 07
54
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
book, full pagewidth
display glass
dot matrix
COLUMN LAYOUT
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
ROW LAYOUT
1 to 8
16 to 9
MLB898
2 lines by 12 characters display
Fig.38 Display example (PCF2114x); 2-lines by 12 characters.
1997 Apr 07
55
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
handbook, full pagewidth
R1 R8
PCF2116 CHIP-ON-GLASS
R9 R16
R17 R24
4 LINE BY 12 CHARACTER
C1
R25 R32
2116
R9 C60
MGA818 - 1
SCL VSS SDA VDD V0 VLCD
Fig.39 Chip on glass application.
1997 Apr 07
56
Philips Semiconductors
Product specification
LCD controller/drivers
19 BONDING PAD LOCATIONS
PCF2116 family
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
handbook, full pagewidth
C2 C3 C4 C5 C6 C7 C8 C9
y
C30 C1 R24 R23 R22 R21 R20 R19 R18 R17 R8 R7 R6 R5 R4 R3 R2 R1 6.99 mm C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45
0 0 DB7 SCL DB6 SDA DB5 V0 VLCD1 DB4 VLCD2 DB3 VLCD3 DB2 C46 C47 C48 C49 C50 C51
x
PCF2114 PCF2116
C52 C53 C54 C55 C56 C57 C58 C59 C60 R32
R11
R13
R14
R15
R26
R28
R29
R12
R/W
V SS2
DB0
R10
V SS1
DB1
SA0
R16
R25
R27
R30
E
T1
R9
OSC
VDD2
VDD1
5.64 mm
R31
RS
MLB969
Chip dimensions: approximately 5.64 x 6.99 mm. Pad area: 0.0121 mm2. Bonding pad dimensions: 110 x 110 m.
Fig.40 Bonding pad locations.
1997 Apr 07
57
Philips Semiconductors
Product specification
LCD controller/drivers
Table 11 Bonding pad locations (dimensions in m) All x/y coordinates are referenced to centre of chip, see Fig.40. SYMBOL OSC DB1 VDD2 DB0 VDD1 SA0 E VSS1 R/W T1 VSS2 RS R9 R10 R11 R12 R13 R14 R15 R16 R25 R26 R27 R28 R29 R30 R31 R32 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 1997 Apr 07 PAD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 x -2445 -2211 -2034 -1806 -1627 -1437 -1245 -1056 -867 -672 -486 -297 77 247 417 587 757 927 1097 1267 1436 1606 1776 1946 2116 2286 2456 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 y -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3300 -3013 -2760 -2590 -2420 -2250 -2080 -1910 -1740 -1570 -1400 -1230 58 SYMBOL C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 PAD 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
PCF2116 family
x 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2626 2339 2169 1999 1829 1659 1489 1319 1149 979 809 639 469 299 129 -245 -415 -585
y -1060 -890 -720 -550 -380 582 752 922 1092 1262 1432 1602 1772 1942 2112 2282 2452 2622 2792 2962 3132 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302
Philips Semiconductors
Product specification
LCD controller/drivers
PCF2116 family
SYMBOL C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 R24 R23 R22 R21 R20 R19 R18 R17 R8 R7 R6 R5 R4 R3 R2 R1 DB7 SCL DB6 SDA DB5 V0 VLCD1 DB4 VLCD2 DB3 VLCD3 DB2
PAD 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116
x -755 -925 -1095 -1265 -1435 -1605 -1775 -1945 -2115 -2285 -2455 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625 -2625
y 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3302 3015 2846 2676 2506 2336 2166 1996 1826 1656 1487 1317 1147 977 807 637 467 297 -290 -479 -716 -976 -1202 -1388 -1580 -1808 -1985 -2213 -2390 -2621
1997 Apr 07
59
Philips Semiconductors
Product specification
LCD controller/drivers
20 PACKAGE OUTLINE LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
PCF2116 family
SOT425-1
c
y X
A 102 103 65 64 ZE
e Q E HE A A2 A 1 (A 3) Lp pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp detail X L
wM
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 Q 0.70 0.58 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7 0o
o
22.15 16.15 21.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-04-02
1997 Apr 07
60
Philips Semiconductors
Product specification
LCD controller/drivers
21 SOLDERING 21.1 Introduction
PCF2116 family
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 21.2 Reflow soldering
Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 21.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
1997 Apr 07
61
Philips Semiconductors
Product specification
LCD controller/drivers
22 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF2116 family
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 23 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 24 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 Apr 07
62
Philips Semiconductors
Product specification
LCD controller/drivers
NOTES
PCF2116 family
1997 Apr 07
63
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
417067/1200/04/pp64
Date of release: 1997 Apr 07
Document order number:
9397 750 01754

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